1. Field of the Invention
The present invention relates to a method of fabricating an embedded DRAM. More particularly, the present invention relates to a method for fabricating an embedded DRAM which integrates a local interconnect process.
2. Description of the Related Art
An embedded DRAM is a device that integrates a memory circuit and a logic circuit into single chip. This design scheme allows the device to have very fast access speed, making the DRAM device useful in data processing systems that require high speed, where large amounts of data are processed.
FIGS. 1A through 1D are schematic, cross-sectional diagrams used to depict steps in a conventional method for fabricating an embedded DRAM.
Referring to FIG. 1A, a memory circuit region 101 and a logic circuit region 119 are formed in a substrate 100, wherein the memory circuit region 101 and the logic circuit region 119 are separated by an isolation region 108. Gates 102, 104 and source/drain regions 110, 112, 114 are formed in the memory circuit region 101, wherein the gates 102 and 104 are neighbors. A gate 106 and source/drain regions 116, 118 are formed in the logic circuit region 119.
Referring to FIG. 1B, a dielectric layer 120 is formed over the substrate 100. A contact hole 122 is formed in the dielectric layer 120 to expose the source/drain region 112. A bit line 124 is formed to electrically couple with the source/drain region 112 through the contact hole 122.
Referring to FIG. 1 C, a dielectric layer 126 is formed over the substrate 100. A contact hole 128 is formed in the dielectric layers 120 and 126 to expose the source/drain region 110. A capacitor 130 is formed to electrically couple with the source/drain region 110 through the contact hole 128. The capacitor 130 includes a bottom electrode 132, a dielectric layer 134 and an upper electrode 136. A dielectric layer 138 is formed over the substrate 100.
Referring to FIG. 1D, contact holes 140, 142 are formed in the dielectric layers 120, 126 and 138 to expose the source/drain region 116 and the gate 106, respectively. An interconnect 144 is formed to electrically couple with the source/drain region 116 and the gate 106 through the contact holes 140 and 142.
The interconnect 144 is formed after forming the capacitor 130. Because plural dielectric layers are formed over the substrate 100, the aspect ratio of the contact holes 140, 142 is high. It is difficult to form the contact holes 140, 142, and thus the interconnect 144 is also difficult to form. Furthermore, the conducting path of the interconnect 144 is too long to decrease the performance of the device.
Through the duration of forming the bit line 124 and the capacitor 130 in the memory circuit region 101, no device is formed in the logic circuit region 119. Thus, the elevation difference of the memory circuit 101 and the logic circuit region 119 is obvious. The subsequent photolithography process is affected.